// Data file for Mano Basic Computer bus, name BUS, size 16, inputCount 7 ram, name M, size 4096 16, control Read Write, destination BUS 7 register, name AR, size 12, control LD INR CLR, destination BUS 1 register, name PC, size 16, control LD INR CLR, destination BUS 2 register, name DR, size 16, control LD INR CLR, destination BUS 3 register, name AC, size 16, control LD INR CLR, destination BUS 4 register, name IR, size 16, control LD , destination BUS 5 register, name TR, size 16, control LD INR CLR, destination BUS 6 register, name OUTR, size 8, control LD register, name INPR, size 8 register, name SC, size 4 register, name CODE, size 3 flag, name I flag, name S flag, name E, ALU CARRY flag, name R flag, name IEN flag, name FGI flag, name FGO // default is output not busy setRegister, FGO, 1 // 10: 1234 ABCD // 30: FF01 00AA // 100: 2107 7200 7020 1106 3108 7001 0053 ffe9 0000 loadRam 21: 083 7001 7001 83: 50 50: b8f2 endLoadRam setRegister, INPR, 8c setRegister, FGI, 0 setRegister, AC, A937 setRegister, E, 1 setRegister, PC, 21 PCStart, PC, 21 RTLinstructions // A note to be ignored 00000, s, t 0, SC 0, IEN 0, R 0, S 1 00001, h, t 0, S 0 00100, f 00000 // output processing 00110, f 00100, c FGO == 0, FGO 1, SimulatorOutput < OUTR, n 00120 00115, f 00100, c FGO != 0, n 00120 00120, f 00110, f 00115 // input processing 00150, f 00120, c SimulatorHasInput == 1, c FGI == 0, FGI 1, INPR < SimulatorInput, SimulatorHasInput 0, n 00200 00151, f 00120, c SimulatorHasInput == 1, c FGI != 0, n 00200 00155, f 00120, c SimulatorHasInput != 1, n 00200 // start main instruction cycle 00200, f 00150, f 00151, f 00155 // interrupt processing - t0 - t2 20000, f 00200, t 0,c R == 1, AR 0, TR < PC, SC ++ 21000, f 20000, t 1, M AR < TR, PC 0, SC ++ 22000, f 21000, t 2, PC ++, IEN 0, R 0, SC 0, n 100 // regular processing - t0 - t2 10000, f 00200, t 0,c R == 0, AR < PC, SC ++ 11000, f 10000, t 1, IR < M AR, PC ++, SC ++ 12000, f 11000, t 2, I < IR 15, CODE < IR 12 14, AR < IR 0 11, SC ++ // instruction decoding 13000, f 12000, t 3,c CODE != 7 13010, f 13000, t 3,c I == 0, SC ++ 13020, f 13000, t 3,c I == 1, AR < M AR, SC ++ // interesting parts of instructions 14000, f 13010, f 13020, t 4,c CODE == 0, DR < M AR, SC ++ 15000, f 14000, t 5, AC < AC ALU_And DR, SC 0, n 100 14010, f 13010, f 13020, t 4,c CODE == 1, DR < M AR, SC ++ 15010, f 14010, t 5, AC < AC ALU_Add DR E, SC 0, n 100 14020, f 13010, f 13020, t 4,c CODE == 2, DR < M AR, SC ++ 15020, f 14020, t 5, AC < DR, SC 0, n 100 14030, f 13010, f 13020, t 4, c CODE == 3, M AR < AC, SC 0, n 100 14040, f 13010, f 13020, t 4, c CODE == 4, PC < AR, SC 0, n 100 14050, f 13010, f 13020, t 4, c CODE == 5, M AR < PC, AR ++, SC ++ 15050, f 14050, t 5, PC < AR, SC 0, n 100 14060, f 13010, f 13020, t 4, c CODE == 6, DR < M AR, SC ++ 15060, f 14060, t 5, DR ++, SC ++ 16060, f 15060, t 6,c DR == 0, M AR < DR, PC ++, SC 0, n 100 16065, f 15060, t 6,c DR != 0, M AR < DR, SC 0, n 100 // I/O (I==1, IR=Fxxx) vs register instructions (IR=7xxx) 13030, f 12000, t 3,c CODE == 7 // Register instructions, 7xxx 13100, f 13030, t 3,c IR == x7800, AC 0, SC 0, n 100 13110, f 13030, t 3,c IR == x7400, E 0, SC 0, n 100 13120, f 13030, t 3,c IR == x7200, AC < AC ALU_Complement, SC 0, n 100 13130, f 13030, t 3,c IR == x7100, E < E ALU_Complement, SC 0, n 100 13140, f 13030, t 3,c IR == x7080, AC < AC ALU_ShiftRightWithCarry E, SC 0, n 100 13150, f 13030, t 3,c IR == x7040, AC < AC ALU_ShiftLeftWithCarry E, SC 0, n 100 13160, f 13030, t 3,c IR == x7020, AC ++, SC 0, n 100 13170, f 13030, t 3,c IR == x7010, c AC 15 == 0, PC ++, SC 0, n 100 13175, f 13030, t 3,c IR == x7010, c AC 15 == 1, SC 0, n 100 13180, f 13030, t 3,c IR == x7008, c AC 15 == 1, PC ++, SC 0, n 100 13185, f 13030, t 3,c IR == x7008, c AC 15 == 0, SC 0, n 100 13190, f 13030, t 3,c IR == x7004, c AC == 0, PC ++, SC 0, n 100 13195, f 13030, t 3,c IR == x7004, c AC != 0, SC 0, n 100 13200, f 13030, t 3,c IR == x7002, c E == 0, PC ++, SC 0, n 100 13205, f 13030, t 3,c IR == x7002, c E != 0, SC 0, n 100 13210, f 13030, t 3,c IR == x7001, SC 0, n 1, // halt // I/O instructions, Fxxx 13220, f 13030, t 3,c IR == xF800, AC 0 7 < INPR, FGI 0, SC 0, n 100 13230, f 13030, t 3,c IR == xF400, OUTR < AC 0 7, FGO 0, SC 0, n 100 13240, f 13030, t 3,c IR == xF200, c FGI == 1, PC ++, SC 0, n 100 13245, f 13030, t 3,c IR == xF200, c FGI != 1, SC 0, n 100 13250, f 13030, t 3,c IR == xF100, c FGO == 1, PC ++, SC 0, n 100 13255, f 13030, t 3,c IR == xF100, c FGO != 1, SC 0, n 100 13260, f 13030, t 3,c IR == xF080, IEN 1, SC 0, n 100 13270, f 13030, t 3,c IR == xF040, IEN 0, SC 0, n 100 endInstructions // Start of next instruction state: InstructionCycleStart, 200 assembler word, bytes 2 format, name f1, words 1, fieldCount 0, codeBits 0 15 format, name f2, words 1, fieldCount 1, codeBits 12 15, f1 0 11 value label format, name f3, words 1, fieldCount 2, codeBits 12 15, f2 0 11 value label AND, f2, 0000 AND, f3, 8000 ADD, f2, 1000 ADD, f3, 9000 LDA, f2, 2000 LDA, f3, A000 STA, f2, 3000 STA, f3, B000 BUN, f2, 4000 BUN, f3, C000 BSA, f2, 5000 BSA, f3, D000 ISZ, f2, 6000 ISZ, f3, E000 CLA, f1, 7800 CLE, f1, 7400 CMA, f1, 7200 CME, f1, 7100 CIR, f1, 7080 CIL, f1, 7040 INC, f1, 7020 SPA, f1, 7010 SNA, f1, 7008 SZA, f1, 7004 SZE, f1, 7002 HLT, f1, 7001 INP, f1, F800 OUT, f1, F400 SKI, f1, F200 SKO, f1, F100 ION, f1, F080 IOF, f1, F040 endAssembler helpComputer ComputerSimulator - Mano basic computer Help
This computer is defined in
Computer System Architecture, 3rd edition
by M. Morris Mano
Published by Prentice-Hall, c 1993
Chapter 5, pp 123-172.

Mano describes the assembly language for this computer in Chapter 6, pp 173-212.

Architecture (pg 157)

  1. A memory unit with 4096 words, 16 bits each
  2. Nine registers, with length in bits in parentheses: AR (12), PC (12), DR (16), AC (16), IR (16), TR (16), OUTR (8), INPR (8), and SC (4).
  3. Seven flip-flops:
    1. I (pg 126) interrupt enable
    2. S (pg 144) stop (0)/go (1)
    3. E (pg 131) carry-out bit from ALU
    4. R (pg 154) interrupt raised
    5. IEN (pg 153) interrupt enabled
    6. FGI (pg 151) input register available
    7. FGO (pg 152) output register available
  4. Two decoders: 3x8 operation decoder, 4x16 timing decoder
  5. A 16-bit common bus
  6. Control logic gates
  7. ALU connected to AC input

The instructions are (pg 133) - defined in detail on pg 159

Type
 Symbol
 Hex code
 Description
 Register Transfer Language
Memory
 AND
 0xxx
 8xxx
 AND memory word with AC
 AC <-- AC and M[xxx] (or M[M[xxx]])
ADD
 1xxx
 9xxx
 ADD memory word with AC
 AC <-- AC + M[xxx] (or M[M[xxx]])
LDA
 2xxx
 Axxx
 Load AC from memory word
 AC <-- M[xxx] (or M[M[xxx]])
STA
 3xxx
 Bxxx
 Store AC to memory word
 M[xxx] <-- AC (or M[M[xxx]])
BUN
 4xxx
 Cxxx
 Branch unconditionally
 PC <-- M[xxx] (or M[M[xxx]])
BSA
 5xxx
 Dxxx
 Branch and save return address
 M[xxx] <-- PC (or M[M[xxx]])
PC <-- M[xxx] + 1
ISZ
 6xxx
 Exxx
 Increment and skip if 0
 M[xxx] <-- M[xxx] + 1 (or M[M[xxx]])
if (M[xxx] = 0) then PC <-- PC + 1
Register
 CLA
 7800
 Clear AC
 AC <-- 0
CLE
 7400
 Clear E
 E <-- 0
CMA
 7200
 Complement AC
 AC <-- not AC (1's complement)
CME
 7100
 Complement E
 E <-- not E
CIR
 7080
 Right circular shift AC and E
 AC (0-14) <-- AC (1-15)
AC (15) <-- E
E <-- AC (0)
CIL
 7040
 Left circular shift AC and E
 AC (1-15) <-- AC (0-14)
AC (0) <-- E
E <-- AC (15)
INC
 7020
 Increment AC
 AC <-- AC + 1
SPA
 7010
 Skip if AC is non-negative
 if (AC(15) = 0) PC <-- PC + 1
SNA
 7008
 Skip if AC is negative
 if (AC(15) = 1) PC <-- PC + 1
SZA
 7004
 Skip if AC is zero
 if (AC = 0) PC <-- PC + 1
SZE
 7002
 Skip if E is zero if (E = 0) PC <-- PC + 1
HLT
 7001
 Halt computer
 S <-- 0
Input/Output
 INP
 F800
 Input character to AC
 AC <-- INPR
OUT
 F400
 Output character to AC
 OUTR <-- AC
SKI
 F200
 Skip on input flag
 if (FGI = 1) PC <-- PC + !
SKO
 F100
 Skip on output flag
 if (FGO = 1) PC <-- PC + 1
ION
 F080
 Interrupt on
 IEN <--- 1
IOF
 F040
 Interrupt off
 IEN <-- 0


endHelp more stuff helpAssembler ComputerSimulator - Mano basic computer Assembly Language Help
This computer is defined in
Computer System Architecture, 3rd edition
by M. Morris Mano
Published by Prentice-Hall, c 1993
Chapter 5, pp 123-172.

Mano describes the assembly language for this computer in Chapter 6, pp 173-212.

General notes:

  1. Format - the label must be in the first column
    <label opt> <code> <address opt> <I opt> [/<comments>]
  2. Pseudo instructions:
    1. SETPCSTART <address>
    2. ORG <address in hex>
    3. END
    4. DEC <data word in decimal, -32768 through 32767>
    5. HEX <data word in HEX, 0000 - FFFF>

Examples:

Subtracting two numbers (pg 181)

/ computing A - B
    SETPCSTART 100
    ORG 100
    LDA SUB  / get B
    CMA      / 1's complement of B
    INC      / 2's complement of B
    ADD MIN  / add A
    STA DIF  / save result
    HLT
MIN DEC 83
SUB DEC -23
DIF HEX 0
    END

Adding an array of 10 number (original is 100, but this example is good enough to get the idea) (pg 191)

    SETPCSTART 100
    ORG 100
    LDA ADS
    STA PTR
    LDA NBR
    STA CTR

LOP ADD PTR I
    ISZ PTR
    ISZ CTR
    BUN LOP
    STA SUM
    HLT

ADS HEX 150
PTR HEX 0
NBR DEC -10
CTR HEX 0
SUM HEX 0

    ORG 150 / array of 10 values
    DEC 23
    DEC 14
    DEC 21
    DEC -16
    DEC 38
    DEC -249
    DEC 103
    DEC 56
    DEC 78
    DEC 93
    END

Subroutine with parameter (pg 201)

/ compute A or B in a subroutine
/ using DeMorgan's law:
/ A or B = (A' and B')'
    SETPCSTART 100
    ORG 100
    LDA X     / put A in AC
    BSA OR    / call subroutine
    HEX 3AF6  / here is B
    STA Y     / result returned in AC
    HLT

X   HEX 7B95
Y   HEX 0

/ A or B = (A' and B')'
OR  HEX 0     / start of subroutine
    CMA       / A'
    STA TMP   / tmp = A'
    LDA OR I  / get B
    CMA       / B'
    AND TMP   / AC <-- A' and B'
    CMA       / (A' and B')'
    ISZ OR    / increment return address, skip parameter
    BUN OR I  / return from subroutine
TMP HEX 0
    END

End of page

endHelp